1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing it, and more particularly to a method for manufacturing a chip size package. The chip size package (CSP) generally refers to a package which has a size approximately equal to or slightly larger than a chip size, and intends high-density mounting on the printed(/circuit) board. The present invention relates to technology for improving reliability of the formation of a metal post adopted for the CSP.
2. Description of the Related Art
In this technical field, previously known are a structure called xe2x80x9cBGA (Ball Grid Array)xe2x80x9d having a plurality of solder balls arranged in a plane, a structure called xe2x80x9cfine pitch BGAxe2x80x9d in which the ball pitch of the BGA is further decreased to reduce the external shape to a chip size, etc.
In recent years, a wafer CSP has been proposed in xe2x80x9cNIKKEI MICRODEVICExe2x80x9d August, 1998, pp 44-71. This wafer CSP is a CSP in which wirings and pads in an array are basically formed in a wafer process (pre-step) before chip dicing. Chip dicing is a step of dividing a plurality of chips by cutting the wafer. This technique is expected that it can integrate the wafer process and package process (post-step) to reduce package cost greatly.
The wafer CSP is classified into a resin-sealing type and a rearrangement wiring type (hereinafter referred to as rewiring type). The resin sealing type has a structure with the surface covered with sealing resin like a conventional package, in which metal posts are formed on a wiring layer on the chip surface and the periphery thereof is sealed with sealing resin.
Generally, it is said that when a package is loaded on a printed board, the stress generated owing to a difference in their thermal expansion coefficient therebetween is concentrated to the metal posts, but the resin sealing type, which has the metal posts with an increased length, can disperse the stress.
On the other hand, the rewiring type has a structure in which rewiring is made without using sealing resin as shown in FIG. 10. Specifically, an Al electrode 52, a wiring layer 53 and an insulating layer 54 are stacked on the surface of a chip, and a metal post 55 is formed on the wiring layer 53. A solder ball 56 is formed on the metal post 55. The wiring layer 53 is used as a rewiring for arranging the solder ball 56 in a prescribed array on the chip.
The resin sealing type in which the metal post with a length increased to about 100 xcexcm is reinforced by sealing resin can acquire great reliability. However, the process of forming sealing resin must be carried out using a mold in a post-step. This complicates the manufacturing process.
On the other hand, the rewiring type has an advantage that the manufacturing process is relatively simple and most steps thereof can be performed in a wafer process. However, it is required to relax the stress by any technique to enhance the reliability.
Where an Al electrode is used, an opening from which the Al electrode 52 exposed is made and at least one layer of barrier metal (not shown) is formed in the opening between the metal post 55 and Al electrode 52, and the solder ball 56 is formed on the metal post 55.
The above prior art of the rewiring type has the following defects.
In the manufacturing process as seen from FIG. 10, polyimide resin is applied to cover the metal post 55 completely, and after having been hardened, its upper surface is ground to expose the head of the metal post 55. Further, after the solder ball 56 is formed on the exposed area, the wafer is diced together with the polyimide resin so that it is divided into individual chips.
Therefore, on the side exposed by dicing, an interface between the insulating layer 51 (e.g. BPSG film) formed below the Al electrode 52 and the insulating resin layer 54 is located. Since the insulating layer has high moisture absorbency, moisture invades from the interface, thus leading deterioration of the resultant element.
Further, there is a difference in the thermal expansion coefficient between the insulating resin layer of e.g. epoxy, and the BPSG film 51, between the insulating layer and an Si3N4 film, between the insulating layer and a SiO2 film , etc. Therefore, when moisture invades the interface, inconvenience such as exfoliation of the insulating resin layer 54 occurred.
The present invention has been accomplished in order to overcome the inconveniences described above.
An object of the present invention is to prevent deterioration of an element when moisture invades an interface owing to a difference in the thermal expansion coefficient between the insulating resin layer of e.g. epoxy, and the BPSG film 51, between the insulating layer and an Si3N4 film, between the insulating layer and a SiO2 film , etc.
In order to attain the above object, the semiconductor device according to the invention is manufactured as follows. First, as seen from FIG. 2, a passivation film 3 having an opening K from which a part of an Al electrode 1 formed through an interlayer insulating film 2 made of a BPSG film is exposed is formed on a wafer. As seen from FIG. 4, a wiring layer 7, which is connected to the Al electrode 1 exposed from the opening K and extended to the upper surface of the wafer, is formed. As seen from FIG. 5, after the metal post 8 is formed on the wiring layer 7, the first groove TC1, which is located on the periphery of a chip inclusive of the wiring layer 7 and half cuts the wafer, is formed. Further, as seen from FIG. 7, the upper portion of the interlayer insulating film 2 is isotropically etched through a first groove TC1 to form the second groove TC2 having a larger opening diameter than that of the first groove TC1. As seen from FIG. 8, the wafer surface inclusive of the wiring layer 7, second groove TC2 and first groove TC1 is resin-sealed to form the insulating resin layer R. Thereafter, as seen from FIG. 9, the solder ball 12 is formed on the metal post 8 exposed from the insulating resin layer R. Finally, the wafer is fully cut through the insulating resin layer R formed in the first and the second grooves TC1 and TC2.